Change Log

This file lists all important changes to ATS9373-D6 Firmware

[34.02] - 2021-09-03

• Fixed timing bug in v34.01 that caused incorrect record lengths in NPT mode. Customers with v34.01 firmware must update to v34.02.

[34.01] - 2021-04-07

• Fixed a bug that was causing intermittent link problems in some computers.

[33.03] - 2021-01-28

• Fixed a bug that caused intermittent data corruption at slow data rates.

[31.12] - 2019-12-09

• Updated NPT footer logic to allow optional fixed 50 MHz timing.

• Also added NPT footer capability in 12-bit packed mode for dual channel acquisition.

[31.09] - 2019-09-26

• Fixed bug whereby overflow was not reported and data was allowed to be written into VFIFO even after an overflow, causing recording of corrupt lossy data.

[31.08] - 2019-05-29

• Improved PCIe signal conditioning.

• Added NPT footer support in 12 bit packed mode.

[30.09] - 2018-12-21

• Improved timing for ADC data capture at 2 GS/s. This is to fix a problem seen with some ADC chips at higher temperatures.

[30.04] - 2018-10-03

• Added protection against false trigegring if trigger source is External and has a frequency higher than one trigger per record. New signal re_trigger_protection (REG58[26]) = '1' will holdoff trigger until record is done.

[30.03] - 2018-08-30

• Fixed bug introduced in FPGA v30.01 that resulted in the possibility of having a corrupt data packet at the start of a DMA buffer.

[30.01] - 2018-07-23

• Uses FFT v5.2 that fixes a bug in REAL_ONLY and IMAG_ONLY outputs.

[28.07] - 2017-08-20

• Fixed a bug in trigger logic that would miss triggers if the source was CHA or CH B. External trigger is not affected, as it was already working properly.

[28.06] - 2017-03-23

• Reduced re-arm time by modifying Trigger logic. Earlier versions of firmware required hundreds of sample clocks for re-arm. Now it is down to 32 points.

[28.05] - 2016-10-17

• Improved DMA circuit for Dual Buffer Mode. FIFO read circuit stops only when used[9..8] = '11'.

[28.04] - 2016-10-15

• Added the ability to read virtual FIFO usage using Register 46. An increasing value can be useful to predict if data consumption is slower than acquisition speed.

• Added circuit that allows user to read out data already acquired in the on-board 8GB DDR3 buffer if an overflow is detected. This is done by deferring the overflow flag until all the data has been read out.

• Removed FIFO flushing after end of trigger enable (B-scan) as that is shown to have caused data corruption problems.

[28.01] - 2016-09-15

• NPT Footer (time domain) now goes into last 8 samples of both CH A buffer & CH B buffer in dual_buffer_mode. Other mode behaves same as before.

[28.00] - 2016-09-13

• Changed dual_buffer_mode bit to be Reg_58[27].

[27.05] - 2016-09-08

• Added additional FIFOs for dual channel mode to get separate, de-interleaved, buffers for each channel.

[27.03] - 2016-08-17

• Added software selectable FPGA based filtering of (Nyquist/2) spur in DES mode. Turned on by writing to Register 52 (in 3 separate commands) 0x0000 0000 , 0x0000 0710 and finally 0x0000 0730. To turn off, write 0x0000 0000 to Register 52.

[27.01] - 2016-06-23

• Updated FFT to v4.7.